The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. At the same time, spacing between devices on a chip also has shrunk to accommodate a greater functional density. For example, in a memory chip such as an SRAM chip, a gate layer is processed to form a line that may be referred to as a gate line. The gate line is divided into multiple portions in a later processing step, each portion froms a gate of a transistor device. The spacing between these divided gate line portions may be referred to as a gate line-end spacing. The gate line-end spacing may be considered a critical dimension (CD) of a chip. To increase the transistor count on the SRAM chip, a smaller CD such as a smaller gate line-end spacing is desired. However, it may be difficult to reduce the critical dimension to a desired size by relying on lithography technologies alone. Other methods of reducing the CD may include a tapered hard mask profile but this suffers drawbacks such as a bridge defect or a mushroom defect, which could cause shorting between transistor devices or otherwise degrade the IC chip's performance.